fpga - How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

Question

Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function*......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation..

module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;


always
begin
#50 Clk=~Clk;
end

 always @(posedge Clk)
     begin
      a=1'b1;
      delay();
      a=1'b0;
      delay();
       a=1'b1;
      end 


  task delay();
   begin
   for(i=0;i==(stmp==4'b1111);i=i+1)
  begin
   @(posedge Clk)
    begin
    stmp=stmp+1;
    end
    end

  if(stmp==4'b1111)
  begin
  stmp=4'b0000;   
  end    

  end
  endtask


    endmodule 

Actually friends I want this a=1'b0; delay(); a=1'b1; please help I already tried delay Generation Using Counter previously but it not works for me.....If you know same using Counter then please tell me......Thanks

Answer 1

// will generate a delay of pow(2,WIDTH) clock cycles 
// between each change in the value of "a"
`define WIDTH 20

reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];

always @(posedge Clk)
  counter <= counter + 1;

You have to choose a suitable value for WIDTH according to how much delay you want between changes in a and the rate of your Clk signal