VHDL: Read input data in a loop

Question

I have state machine where I read 72-bit input data (8-bit command and 64-bit argument) in 8-bit chunks:

                when IDLE =>
                
                    if i_DataAvailable_n = '0' then
                        cmd_st <= C;
                        o_DataGet <= '1';                   
                        cmd <= i_DataInput;
                    else
                        cmd_st <= IDLE;
                        o_DataGet <= '0';
                        cmd <= (others => '0');
                        argument <= (others => '0');
                    end if;
      
                ------------------------------------------
                when C =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= A1;
                        o_DataGet <= '1';                        
                        argument(7 downto 0) <= i_DataInput;
                    else
                        cmd_st <= C;
                        o_DataGet <= '0';                        
                        argument(7 downto 0) <= (others => '0');
                    end if;
                ------------------------------------------
                when A1 =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= A2;
                        o_DataGet <= '1';                        
                        argument(15 downto 8) <= i_DataInput;
                    else
                        cmd_st <= A1;
                        o_DataGet <= '0';                        
                        argument(15 downto 8) <= (others => '0');
                    end if;
                ------------------------------------------
                when A2 =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= A3;
                        o_DataGet <= '1';                        
                        argument(23 downto 16) <= i_DataInput;
                    else
                        cmd_st <= A2;
                        o_DataGet <= '0';                        
                        argument(23 downto 16) <= (others => '0');
                    end if; 
                ------------------------------------------
                when A3 =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= A4;
                        o_DataGet <= '1';                        
                        argument(31 downto 24) <= i_DataInput;
                    else
                        cmd_st <= A3;
                        o_DataGet <= '0';                        
                        argument(31 downto 24) <= (others => '0');
                    end if; 
                 ------------------------------------------
                 when A4 =>
                 if i_DataAvailable_n = '0' then
                     cmd_st <= A5;
                     o_DataGet <= '1';                        
                     argument(39 downto 32) <= i_DataInput;
                 else
                     cmd_st <= A4;
                     o_DataGet <= '0';                        
                     argument(39 downto 32) <= (others => '0');
                 end if;
                ------------------------------------------
                when A5 =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= A6;
                        o_DataGet <= '1';                        
                        argument(47 downto 40) <= i_DataInput;
                    else
                        cmd_st <= A5;
                        o_DataGet <= '0';                        
                        argument(47 downto 40) <= (others => '0');
                    end if; 
                ------------------------------------------
                when A6 =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= A7;
                        o_DataGet <= '1';                        
                        argument(55 downto 48) <= i_DataInput;
                    else
                        cmd_st <= A6;
                        o_DataGet <= '0';                        
                        argument(55 downto 48) <= (others => '0');
                    end if;                    
                ------------------------------------------
                when A7 =>
                    if i_DataAvailable_n = '0' then
                        cmd_st <= EXE;
                        o_DataGet <= '1';                        
                        argument(63 downto 56) <= i_DataInput;
                    else
                        cmd_st <= A7;
                        o_DataGet <= '0';                        
                        argument(63 downto 56) <= (others => '0');
                    end if;                    
                    

                when EXE =>
                    <... rest of the code ...>

Is in VHDL some more clever solution for it which doesn not require so many states? Kind of loop in which the incoming byte could append to the proper argument position?

Answer 1

等待大神答复